For a Testability Analysis the following is required:

• elektrical schematics
• Layout-data (in a ASCII exchange format like e.g. GenCad, ODB++,...)
  alternatively at least a Netlist and  Testpoint liste or list of the accessible nodes
• Bill of Material/BOM (Text, Excel, ..., not as PDF), if applicable multiple BOMs for multiple Variants (might be included in ODB)
• Test Strategies used (and their configuration)
• How do you need the results (Excel, HTML-Files, ...)
• Is the Layout frozen or are improvements/modifications still possible
• Do you prefer a presentation/meeting for the results or only need the files

Optional:

• Test spectiification for functional tests (if applicable, and INCLUDING a Fault Dictionary!)
• Which test techniques do you use (e.g. test Connectors or ICs with capacitive techniques, Boundary-Scan,...)

Additional hints:

• all Data should be exported directly from the layout tool, Data converted with by 3rd party Tools usually contain less informatione!
• in many cases the vendor's own formats  (e.g. PCF/DSGF/FTF for Zuken) or GenCad may contain more information compared to generic formats like ODB++ (which is by the way a very poor data format)